#ChipScope Core Inserter Project File Version 3.0
#Fri Mar 13 18:30:59 CST 2015
Project.device.designInputFile=D\:\\GitHub\\VHDL_Modules\\Wings_test\\Wings_test_cs.ngc
Project.device.designOutputFile=D\:\\GitHub\\VHDL_Modules\\Wings_test\\Wings_test_cs.ngc
Project.device.deviceFamily=13
Project.device.enableRPMs=true
Project.device.outputDirectory=D\:\\GitHub\\VHDL_Modules\\Wings_test\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=0
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=512
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
